74ls138 decoder multiplexer The 74AHC/AHCT138 are high-speed Si-gate CMOS devices and are pincompatible with low power Schottky TTL (LSTTL). They are specified incompliance with JEDEC standard No. 7A.The 74AHC/AHCT138 decoders accept three binary weighted address inputs(A0,A1and A2) and when enabled, provide 8 mutually exclusive active LOWoutputs (Y0toY7).The ‘138’ features three enable inputs: two active LOW (E1andE2) and oneactive HIGH (E3). Every output will be HIGH unlessE1andE2are LOW and E3is HIGH.This multiple enable function allows easy parallel expansion of the ‘138’ to a1-of-32 (5 to 32 lines) decoder with just four ‘138’ ICs and one inverter.The ‘138’ can be used as an eight output demultiplexer by using one of theactive LOW enable inputs as the data input and the remaining enable inputs asstrobes. Unused enable inputs must be permanently tied to their appropriateactive HIGH or LOW state.The ‘138’ is identical to the ‘238’ but has inverting outputs.
datasheet here<----------
datasheet here<----------
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