The CD4041UB/CD4041UBC is a quad true/complementbuffer consisting of N- and P-channel enhancement modetransistors having low-channel resistance and high current(sourcing and sinking) capability. The CD4041 is intendedfor use as a buffer, line driver, or CMOS-to-TTL driver.All inputs are protected from static discharge by diodeclamps to VDDand VSS.

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The 4N25 family is an industry standard single channelphototransistor coupler. This family includes the 4N25,4N26, 4N27, 4N28. Each optocoupler consists of galliumarsenide infrared LED and a silicon NPN phototransistor.

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general purpose operational amplifier

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These 8-bit registers feature totem-pole 3-STATE outputsdesigned specifically for driving highly-capacitive or rela-tively low-impedance loads. The high-impedance state andincreased high-logic level drive provide these registers withthe capability of being connected directly to and driving thebus lines in a bus-organized system without need for inter-face or pull-up components. They are particularly attractivefor implementing buffer registers, I/O ports, bidirectional busdrivers, and working registers

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bcd to 7 segment driver

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The CD4047B is capable of operating in either themonostable or astable mode. It requires an external capac-itor (between pins 1 and 3) and an external resistor(between pins 2 and 3) to determine the output pulse widthin the monostable mode, and the output frequency in theastable mode.Astable operation is enabled by a high level on the astableinput or low level on the astable input. The output fre-quency (at 50% duty cycle) at Q and Q outputs is deter-mined by the timing components. A frequency twice that ofQ is available at the Oscillator Output; a 50% duty cycle isnot guaranteed.Monostable operation is obtained when the device is trig-gered by LOW-to-HIGH transition at + trigger input orHIGH-to-LOW transition at − trigger input. The device canbe retriggered by applying a simultaneous LOW-to-HIGHtransition to both the + trigger and retrigger inputs.A high level on Reset input resets the outputs Q to LOW, Qto HIGH.

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The 74AHC/AHCT138 are high-speed Si-gate CMOS devices and are pincompatible with low power Schottky TTL (LSTTL). They are specified incompliance with JEDEC standard No. 7A.The 74AHC/AHCT138 decoders accept three binary weighted address inputs(A0,A1and A2) and when enabled, provide 8 mutually exclusive active LOWoutputs (Y0toY7).The ‘138’ features three enable inputs: two active LOW (E1andE2) and oneactive HIGH (E3). Every output will be HIGH unlessE1andE2are LOW and E3is HIGH.This multiple enable function allows easy parallel expansion of the ‘138’ to a1-of-32 (5 to 32 lines) decoder with just four ‘138’ ICs and one inverter.The ‘138’ can be used as an eight output demultiplexer by using one of theactive LOW enable inputs as the data input and the remaining enable inputs asstrobes. Unused enable inputs must be permanently tied to their appropriateactive HIGH or LOW state.The ‘138’ is identical to the ‘238’ but has inverting outputs.

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The μA723 is a precision integrated-circuitvoltage regulator, featuring high ripple rejection,excellent input and load regulation, excellent temperature stability, and low standby current. The circuit consistsof a temperature-compensated reference-voltage amplifier, an error amplifier, a 150-mA output transistor, andan adjustable-output current limiter.The μA723 is designed for use in positive or negative power supplies as a series, shunt, switching, or floatingregulator. For output currents exceeding 150 mA, additional pass elements can be connected as shown inFigures 4 and 5.The μA723C is characterized for operation from 0°C to 70°C

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The B Series logic gates are constructed with P and N channelenhancement mode devices in a single monolithic structure(Complementary MOS). Their primary use is where low powerdissipation and/or high noise immunity is desired.

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